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features ? high performance, low power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 130 powerful instructions ? mo st single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16mips throughput at 16mhz (atmega165pa/645p) ? up to 20mips throughput at 20mhz (atmega165a/325a/325pa/645a/3250a/3250pa/6450a/6450p) ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? in-system self-programmable flash program memory ? 16kbytes (atmega165a/atmega165pa) ? 32kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 64kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ?eeprom ? 512bytes (atmega165a/atmega165pa) ? 1kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 2kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ?internal sram ? 1kbytes (atmega165a/atmega165pa) ? 2kbytes (atmega325a/atmega325pa/atmega3250a/atmega3250pa) ? 4kbytes (atmega645a/atmega645p/atmega6450a/atmega6450p) ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25 c (1) ? optional boot code section with independent lock bits ? in-system programming by on-chip boot program ? true read-while-write operation ? programming lock for software security ? qtouch ? library support ? capacitive touch buttons, sliders and wheels ? qtouch and qmatrix acquisition ? up to 64 sense channels ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, and lock bits through the jtag interface ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? four pwm channels ? 8-channel, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? universal serial interface with start condition detector ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise reduct ion, power-save, power-down, and standby ? i/o and packages ? 54/69 programmable i/o lines ? 64/100-lead tqfp, 64-pad qfn/mlf and 64-pad drqfn ? speed grade: ? atmega 165a/165pa/645a/645p: 0 - 16mhz @ 1.8 - 5.5v ? atmega325a/325pa/3250a/3250pa/6450a /6450p: 0 - 20mhz @ 1.8 - 5.5v ? temperature range: ?-40c to 85 c industrial ? ultra-low power consumption (picopower devices) ? active mode: ? 1mhz, 1.8v: 215a ? 32khz, 1.8v: 8a (including oscillator) ? power-down mode: 0.1a at 1.8v ? power-save mode: 0.6a at 1.8v (including 32khz rtc note: 1. reliability qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 8-bit atmel microcontroller with 16/32/64k bytes in-system programmable flash atmega165a atmega165pa atmega325a atmega325pa atmega3250a atmega3250pa atmega645a atmega645p atmega6450a atmega6450p summary rev 8285ds?avr?06/11
2 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 1. pin configurations 1.1 pinout - tqfp and qfn/mlf figure 1-1. 64a (tqfp)and 64m1 (qfn/mlf) pinout atmega165a/atmega165pa/atmega325a/atmega325pa/atmega645a/atmega645p note: the large center pad underneath the qfn/mlf packages is made of metal and internally connected to gnd. it should be sol- dered or glued to the board to ensure good mechanical stability. if the center pad is left unconnected, the package might loose n from the board. 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 pc0 vcc gnd pf0 (adc0) pf7 (adc7/tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) aref gnd avcc (rxd/pcint0) pe0 (txd/pcint1) pe1 dnc (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc2a/pcint15) pb7 (t1) pg3 (oc1b/pcint14) pb6 (t0) pg4 (oc1a/pcint13) pb5 pc1 pg0 pd7 pc2 pc3 pc4 pc5 pc6 pc7 pa7 pg2 pa6 pa5 pa4 pa3 pa0 pa1 pa2 pg1 pd6 pd5 pd4 pd3 pd2 (int0) pd1 (icp1) pd0 (tosc1) xtal1 (tosc2) xtal2 reset/pg5 gnd vcc index corner
3 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 1.2 pinout - 100a (tqfp) figure 1-2. pinout atmega3250a/atmega3250pa/atmega6450a/atmega6450p (oc2a/pcint15) pb7 dnc (t1) pg3 (t0) pg4 reset/pg5 vcc gnd (tosc2) xtal2 (tosc1) xtal1 dnc dnc (pcint26) pj2 (pcint27) pj3 (pcint28) pj4 (pcint29) pj5 (pcint30) pj6 dnc (icp1) pd0 (int0) pd1 pd2 pd3 pd4 pd5 pd6 pd7 avcc agnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) dnc dnc ph7 (pcint23) ph6 (pcint22) ph5 (pcint21) ph4 (pcint20) dnc dnc gnd vcc dnc pa0 pa1 pa2 pa3 pa4 pa 5 pa6 pa7 pg2 pc7 pc6 dnc ph3 (pcint19) ph2 (pcint18) ph1 (pcint17) ph0 (pcint16) dnc dnc dnc dnc pc5 pc4 pc3 pc2 pc1 pc0 pg1 pg0 index corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 dnc (rxd/pcint0) pe0 (txd/pcint1) pe1 (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 vcc gnd dnc (pcint24) pj0 (pcint25) pj1 dnc dnc dnc dnc (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc1a/pcint13) pb5 (oc1b/pcint14) pb6 tqfp
4 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 2. overview the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p is a low-power cmos 8-bit microcon- troller based on the avr enhanced risc architecture. by exec uting powerful instructions in a single clock cycle, this microcontroller achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. program cou n ter i n ter n al oscillator watchdog timer stack poi n ter program flash mcu co n trol register sram ge n eral purpose registers i n structio n register timer/ cou n ters i n structio n decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timi n g a n d co n trol oscillator i n terrupt u n it eeprom spi usart status register z y x alu portb dri v ers porte dri v ers porta dri v ers portf dri v ers portd dri v ers portc dri v ers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 v cc g n d xtal1 xtal2 co n trol li n es + - a n alog comparator pc0 - pc7 8 -bit data bus reset calib. osc data dir. reg. portc data register portc o n -chip debug jtag tap programmi n g logic bou n dary- sca n data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg dri v ers pg0 - pg4 ag n d aref a v cc u n i v ersal serial i n terface a v r cpu porth dri v ers ph0 - ph7 data dir. reg. porth data register porth portj dri v ers pj0 - pj6 data dir. reg. portj data register portj
5 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p the atmega165a/165pa/325a/325pa/3250a/3250pa/ 645a/645p/6450a/6450p provides the following features: 16k/32k/64k bytes of in-system programmable flash with read- w hile- w rite capabilities, 512/1k/2k bytes eeprom, 1k/2k/4k byte sram, 54/ 69 general purp ose i/o lines, 32 general purpose working registers, a jtag interface for boundary-scan, on-chip debugging support and programming, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial interface with start condi- tion detector, an 8-channel, 10-bit adc, a programmable w atchdog timer with internal oscillator, an spi serial port, and five software selectable power saving modes. the idle mode stops the cpu while allo wing the sram, timer/counters, spi port, and interrupt system to con- tinue functioning. the power-do wn mode saves the register cont ents but freeze s the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o mod- ules except asynchronous timer and adc, to mi nimize switching noise during adc conversions. in standby mode, the crys tal/resonator oscillator is running while the rest of the device is sleep- ing. this allows very fast start-up combined with low-power consumption. atmel offers the qtouch ? library for embedding capacitive t ouch buttons, sliders and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the applic ation flash memory. software in the boot flash section will continue to run while the application fl ash section is updated, providing true read- w hile- w rite operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel devise is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p avr is sup- ported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in -circuit emulators, and evaluation kits.
6 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 2.2 comparison between atmega165a/165pa/325a/325pa/3250a/ 3250pa/645a/645 p/6450a/6450p 2.3 pin descriptions 2.3.1 vcc digital supply voltage. 2.3.2 gnd ground. 2.3.3 port a (pa7:pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port b? on page 76 . 2.3.4 port b (pb7:pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving capabilities than the other ports. port b also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port b? on page 76 . table 2-1. differences between: atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p device flash eeprom ram mhz atmega165a 16kbyte 512bytes 1kbyte 16 atmega165pa 16kbyte 512bytes 1kbyte 16 atmega325a 32kbyte 1kbyte 2kbyte 20 atmega325pa 32kbyte 1kbyte 2kbyte 20 atmega3250a 32kbytes 1kbyte 2kbyte 20 atmega3250pa 32kbyte 1kbyte 2kbyte 20 atmega645a 64kbyte 2kbyte 4kbyte 16 atmega645p 64kbyte 2kbyte 4kbyte 16 atmega6450a 64kbyte 2kbyte 4kbyte 20 atmega6450p 64kbyte 2kbyte 4kbyte 20
7 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 2.3.5 port c (pc7:pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port d? on page 79 . 2.3.6 port d (pd7:pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port d? on page 79 . 2.3.7 port e (pe7:pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on ?alter- nate functions of port e? on page 80 . 2.3.8 port f (pf7:pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capa bility. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are ac tivated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7( tdi), pf5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface, see ?alternate functions of port f? on page 82 . 2.3.9 port g (pg5:pg0) port g is a 6-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are extern ally pulled low will sour ce current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running.
8 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p port g also serves the functions of various special features of the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6450p as listed on page 84 . 2.3.10 port h (ph7:ph0) port h is a 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port h output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port h pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port h pins are tri-stated when a reset condition becomes active, even if the clock is not running. port h also serves the functions of various special features of the atmega3250a/3250pa/6450a/6450p as listed on page 85 . 2.3.11 port j (pj6:pj0) port j is a 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port j output buffers have symmetrical drive characteristics with both high sink and source capa- bility. as inputs, port j pins that are externally pulled low will source current if the pull-up resistors are activated. the port j pins are tr i-stated when a reset condition becomes active, even if the clock is not running. port j also serves the functions of various special features of the atmega3250a/3250pa/6450a/6450p as listed on page 87 . 2.3.12 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 28-13 on page 328 . shorter pulses are not guaranteed to generate a reset. 2.3.13 xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. 2.3.14 xtal2 output from the invert ing oscillator amplifier. 2.3.15 avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.3.16 aref this is the analog reference pin for the a/d converter.
9 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. these code examples assume that the part specific header file is included before compilation. for i/o registers located in extended i/o map, "i n", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced with instructio ns that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbrc", "sbr", and "cbr". 6. capacitive touch sensing the atmel qtouch library provides a simple to us e solution to realize touch sensitive interfaces on most atmel avr microcontrollers. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
10 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 7. register summary note: registers with bold type only available in atmega3250a/3250pa/6450a/6450p. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) reserved (0xf9) reserved (0xf8) reserved (0xf7) reserved (0xf6) reserved (0xf5) reserved (0xf4) reserved (0xf3) reserved (0xf2) reserved (0xf1) reserved (0xf0) reserved (0xef) reserved (0xee) reserved (0xed) reserved (0xec) reserved (0xeb) reserved - - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved - - - - - - - - (0xe7) reserved (0xe6) reserved (0xe5) reserved (0xe4) reserved (0xe3) reserved - - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - - (0xe0) reserved - - - - - - - - (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) portj - portj6 portj5 portj4 portj3 portj2 portj1 portj0 93 (0xdc) ddrj - ddj6 ddj5 ddj4 ddj3 ddj2 ddj1 ddj0 93 (0xdb) pinj - pinj6 pinj5 pinj4 pinj3 pinj2 pinj1 pinj0 93 (0xda) porth porth7 porth6 porth5 porth4 porth3 porth2 porth1 porth0 92 (0xd9) ddrh ddh7 ddh6 ddh5 ddh4 ddh3 ddh2 ddh1 ddh0 93 (0xd8) pinh pinh7 pinh6 pinh5 pinh 4 pinh3 pinh2 pinh1 pinh0 93 (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) reserved - - - - - - - - (0xcd) reserved - - - - - - - - (0xcc) reserved - - - - - - - - (0xcb) reserved - - - - - - - - (0xca) reserved - - - - - - - - (0xc9) reserved - - - - - - - - (0xc8) reserved - - - - - - - - (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 data register 193 (0xc5) ubrr0h usart0 baud rate register high 197
11 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p (0xc4) ubrr0l usart0 baud rate register low 197 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c - umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 195 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen 0 txen0 ucsz02 rxb80 txb80 194 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 193 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - (0xbd) reserved - - - - - - - - (0xbc) reserved - - - - - - - - (0xbb) reserved - - - - - - - - (0xba) usidr usi data register 206 (0xb9) usisr usisif usioif usipf usidc us icnt3 usicnt2 usicnt1 usicnt0 206 (0xb8) usicr usisie usioie usi w m1 usi w m0 usics1 usics0 usiclk usitc 207 (0xb7) reserved - - - - - - - - (0xb6) assr - - - exclk as2 tcn2ub ocr2ub tcr2ub 157 (0xb5) reserved - - - - - - - - (0xb4) reserved - - - - - - - - (0xb3) ocr2a timer/counter 2 output compare register a 156 (0xb2) tcnt2 timer/counter2 156 (0xb1) reserved - - - - - - - - (0xb0) tccr2a foc2a w gm20 com2a1 com2a0 w gm21 cs22 cs21 cs20 154 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) reserved - - - - - - - - (0x9a) reserved - - - - - - - - (0x99) reserved - - - - - - - - (0x98) reserved - - - - - - - - (0x97) reserved - - - - - - - - (0x96) reserved - - - - - - - - (0x95) reserved - - - - - - - - (0x94) reserved - - - - - - - - (0x93) reserved - - - - - - - - (0x92) reserved - - - - - - - - (0x91) reserved - - - - - - - - (0x90) reserved - - - - - - - - (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 output compare register b high 134 (0x8a) ocr1bl timer/counter1 output compare register b low 134 (0x89) ocr1ah timer/counter1 output compare register a high 134 (0x88) ocr1al timer/counter1 output compare register a low 134 (0x87) icr1h timer/counter1 input capture register high 135 (0x86) icr1l timer/counter1 input capture register low 135 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p (0x85) tcnt1h timer/counter1 high 134 (0x84) tcnt1l timer/counter1 low 134 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?133 (0x81) tccr1b icnc1 ices1 ? w gm13 w gm12 cs12 cs11 cs10 132 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? w gm11 w gm10 130 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d 213 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 231 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 227 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 231 (0x7a) adcsra aden adsc adate adi f adie adps2 adps1 adps0 229 (0x79) adch adc data register high 230 (0x78) adcl adc data register low 230 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) pcmsk3 ? pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 66 (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 157 (0x6f) timsk1 ? -icie1 ? ? ocie1b ocie1a toie1 135 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 107 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 67 (0x6c) pcmsk1 pcint15 pcint14 pcint13 pcint 12 pcint11 pcint10 pcint9 pcint8 66 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcin t4 pcint3 pcint2 pcint1 pcint0 67 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ? ? ?isc01isc0064 (0x68) reserved ? ? ? ? ? ? ? ? (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register [cal7:0] 37 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr ? ? ? ? prtim1 prspi psusart0 pradc 45 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 37 (0x60) w dtcr ? ? ? w dce w de w dp2 w dp1 w dp0 53 0x3f (0x5f) sreg i t h s v n z c 12 0x3e (0x5e) sph stack pointer high 15 0x3d (0x5d) spl stack pointer low 15 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie r ww sb ?r ww sre blbset pg w rt pgers spmen 283 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd bods bodse pud ? ? ivsel ivce 61/90/267 0x34 (0x54) mcusr ? ? ?jtrf w drf borf extrf porf 53 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se 53 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 o cdr4 ocdr3 ocdr2 ocdr1 ocdr0 238 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 212 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 168 0x2d (0x4d) spsr spif w col ? ? ? ? ? spi2x 167 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 166 0x2b (0x4b) gpior2 general purpose i/o register 27 0x2a (0x4a) gpior1 general purpose i/o register 27 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) reserved ? ? ? ? ? ? ? ? 0x27 (0x47) ocr0a timer/counter0 output compare a 107 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. w hen using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. w hen addressing i/o registers as data space using ld and st instruct ions, 0x20 must be added to these addresses. the atmega165a/165pa/325a/325pa/3250a/3250pa/645a/645p/6450a/6 450p is a complex microcontroller with more periph- eral units than can be supported within the 64 location rese rved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x26 (0x46) tcnt0 timer/counter0 107 0x25 (0x45) reserved ? ? ? ? ? ? ? ? 0x24 (0x44) tccr0a foc0a w gm00 com0a1 com0a0 w gm01 cs02 cs01 cs00 105 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr10 139/158 0x22 (0x42) eearh ? ? ? ? ? eeprom address register high 26 0x21 (0x41) eearl eeprom address register low 26 0x20 (0x40) eedr eeprom data register 26 0x1f (0x3f) eecr ? ? ? ? eerie eem w eee w eeere 27 0x1e (0x3e) gpior0 general purpose i/o register 28 0x1d (0x3d) eimsk pcie pcie2 pcie1 pcie0 ? ? ?int064 0x1c (0x3c) eifr pcif3 pcif2 pcif1 pcif0 ? ? ? intf0 65 0x1b (0x3b) reserved ? ? ? ? ? ? ? ? 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ?ocf2atov2157 0x16 (0x36) tifr1 ? ?icf1 ? ?ocf1bocf1atov1136 0x15 (0x35) tifr0 ? ? ? ? ? ?ocf0atov0139 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 92 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 92 0x12 (0x32) ping ? ? ping5 ping4 ping3 ping2 ping1 ping0 92 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 92 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 92 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 92 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 91 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 91 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 92 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 91 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 91 0x09 (0x29) pind pind7 pind6 pind5 pind4 p ind3 pind2 pind1 pind0 91 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 91 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 91 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 p inc3 pinc2 pinc1 pinc0 91 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 90 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 90 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 90 0x02 (0x22) p o rta p o rta 7 p o rta 6 p o rta 5 p o rta 4 p o rta 3 p o rta 2 p o rta 1 p o rta 0 9 0 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 90 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 90 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
14 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 8. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adi w rdl,k add immediate to w ord rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbi w rdl,k subtract immediate from w ord rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 ? (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 ? (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2
15 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 s w ap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 mov w rd, rr copy register w ord rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 mnemonics operands description operation flags #clocks
16 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 w dr w atchdog reset (see specific descr. for w dr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
17 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9. ordering information 9.1 atmega165a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel 5. see appendix a - atmega165a/165pa/ 325p/3250p specification at 105c speed (mhz) (3) power supply ordering code (2) package (1) operation range 16 1.8 - 5.5v atmega165a-au atmega165a-aur (4) atmega165a-mu atmega165a-mur (4) atmega165a-mch atmega165a-mchr (4) 64a 64a 64m1 64m1 64mc 64mc industrial (-4 0 c to 85 c) atmega165a-an atmega165a-anr (4) atmega165a-mn atmega165a-mnr (4) 64a 64a 64m1 64m1 extended (-4 0 c to 105 c) (5) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 64mc 64-lead (2-row staggered), 7 x 7 x 1.0 mm body, 4.0 x 4.0mm exposed pad, quad flat no-lead package (qfn)
18 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.2 atmega165pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel. 5. see appendix a - atmega165a/165pa/ 325p/3250p specification at 105c. speed (mhz) (3) power supply ordering code (2) package (1) operation range 16 1.8 - 5.5v atmega165pa-au atmega165pa-aur (4) atmega165pa-mu atmega165pa-mur (4) atmega165pa-mch atmega165pa-mchr (4) 64a 64a 64m1 64m1 64mc 64mc industrial (-4 0 c to 85 c) atmega165pa-an atmega165pa-anr (4) atmega165pa-mn atmega165pa-mnr (4) 64a 64a 64m1 64m1 extended (-4 0 c to 105 c) (5) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf) 64mc 64-lead (2-row staggered), 7 x 7 x 1.0mm body, 4.0 x 4. 0 mm exposed pad, quad flat no-lead package (qfn)
19 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.3 atmega325a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega325a-au atmega325a-aur (4) atmega325a-mu atmega325a-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf)
20 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.4 atmega325pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega325pa-au atmega325pa-aur (4) atmega325pa-mu atmega325pa-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf)
21 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.5 atmega3250a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega3250a-au atmega3250a-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp)
22 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.6 atmega3250pa notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.5 - 5.5v atmega3250pa-au atmega3250pa-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp)
23 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.7 atmega645a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega645a-au atmega645a-aur (4) atmega645a-mu atmega645a-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf)
24 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.8 atmega645p notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega645p-au atmega645p-aur (4) atmega645p-mu atmega645p-mur (4) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0mm) plastic gull w ing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/ mlf)
25 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.9 atmega6450a notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega6450a-au atmega6450a-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp)
26 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 9.10 atmega6450p notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging, complies to the european directive for restriction of hazardous subst ances (rohs directive). also halide free and fully green. 3. for speed vs. v cc , see figure 28-1 on page 326 . 4. tape & reel speed (mhz) (3) power supply ordering code (2) package (1) operation range 20 1.8 - 5.5v atmega6450p-au atmega6450p-aur (4) 100a 100a industrial (-4 0 c to 85 c) package type 100a 100-lead, 14 x 14 x 1.0mm, 0.5m m lead pitch, thin profile pl astic quad flat package (tqfp)
27 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 10. packaging information 10.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 64a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1.this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
28 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 10.2 64m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, h 64m1 2010-10-19 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 notes: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 2. dimension and tolerance conform to asmey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf) 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, h 64m1 2010-10-19 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 notes: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 2. dimension and tolerance conform to asmey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf)
29 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 10.3 64mc title drawing no. gpc rev. packa g e drawin g contact: packagedrawings@atmel.com 64mc zxc a 64mc, 64qfn (2-row staggered), 7 x 7 x 1.00 mm body, 4.0 x 4.0 mm exposed pad, quad flat no lead package 10/3/07 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.23 0.28 c 0.20 ref d 6.90 7.00 7.10 d2 3.95 4.00 4.05 e 6.90 7.00 7.10 e2 3.95 4.00 4.05 et ? 0.65 ? er ? 0.65 ? k 0.20 ? ? (ref) l 0.35 0.40 0.45 y 0.00 ? 0.075 s ide view top view bottom view note: 1. the terminal #1 id is a laser-marked feature . pin 1 id d e a1 a y c et/2 r0.20 0.40 b1 a1 b30 a34 b a8 b7 et d2 b16 a18 b22 a25 e2 k (0.1) ref b8 a9 (0.18) ref l b15 a17 l er a26 b23 et
30 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 10.4 100a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 100a, 100-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.5 mm lead pitch, thin profile plastic quad flat package (tqfp) d 100a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.17 ? 0.27 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.50 typ notes: 1. this package conforms to jedec reference ms-026, variation aed. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.08 mm maximum. common dimen s ion s (unit of measure = mm) s ymbol min nom max note
31 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 11. errata 11.1 atmega165a/165pa/325a/ 325pa/3250a/3250pa/645a/645 p/6450a/6450p rev. g no known errata. 11.2 atmega165a/165pa/325a/325p a/3250a/3250pa/645a/645p/6 450a/6450p rev. a to f not sampled.
32 8285ds?avr?06/11 atmega165a/pa/325a/pa/3250a/pa/645a/p/6450a/p 12. datasheet revision history please note that the referring page numbers in this section are referring to this document. the referring revisions in this section are referring to the document revision. 12.1 8285d ? 06/11 12.2 8285c ? 06/11 12.3 8285b ? 03/11 12.4 8285a ? 09/10 1. removed ?preliminary? from the front page. 1. updated ?signature bytes? on page 288 . a, p and pa devices have different signature (0x002) bytes. 2. updated ?dc characteristics? on page 319 for all devices. 1. updated the datasheet according to the atmel new brand style guide 2. updated ?signature bytes? , table 27.3 on page 288 . 3. updated the power supply voltage (1.5 - 5.5v) for all devices in ?ordering information? on page 17 . 4. added ?ordering information? for extended temperature (-40c to 105c) 1. initial revision (based on the atmega165p/325p/32 50p/645/6450/v). 2. changes done compared to atmega165 p/325p/3250p/645/6450/v datasheet: ? new eimsk and eifr register overview ? new graphics in ?typical characteristics? on page 334 . ? ordering information includes tape & reel ?new ?ordering information? on page 17 . ? qtouch library support features
8285ds?avr?06/11 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel : (+81)(3) 3523-3551 fax : (+81)(3) 3523-7581 ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , qtouch ? , qmatrix ? , avr studio ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. w indows ? and others are registered trademarks of microsoft corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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